This invention generally relates to Smart Power integrated circuits and, more particularly, to means and methods for reducing substrate leakage currents associated with RESURF LDMOSFETs employed in such integrated circuits.
There are many integrated circuit (IC) applications today which use metal oxide semiconductor field effect transistor (MOSFET) devices, and include structures in connection with RESURF devices. “RESURF” is an abbreviation standing for “reduced surface field.” RESURF devices and methods are described for example, in U.S. Pat. Nos. 6,882,023 B2 to Khemka et al and 6,747,332 B2 to de Fresart et al.
The presence of a parasitic NPN transistor in a standard isolated RESURF LDMOSFET causes principal current conduction of the device to go through the N-type buried layer (NBL). A voltage drop (or IR drop) in the NBL can turn-on the NBL/substrate diode. As a result, this requires the LDMOSFET device to be broken up into several small sections with an isolation (ISO) tie to the NBL disposed in between at regular intervals.
Accordingly, there is a need for an improved LDMOSFET method and apparatus for overcoming the problems in the art as discussed above.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present disclosure.